LRM Bridge: Datatypes

How to Read This Lesson

This lesson is an LRM bridge. We translate standard language into the questions you actually ask while debugging and reviewing models.

SystemC provides specialized hardware datatypes because standard C++ types (int, bool) cannot natively model arbitrary bus widths, 4-state logic (X/Z states), or bit-level slicing.

Let's look into the Accellera kernel datatypes (sc_dt namespace) to understand how these abstract concepts are implemented using underlying C++ constructs.

Source and LRM Trail

This chapter is the LRM bridge. The primary reference is Docs/LRMs/SystemC_LRM_1666-2023.pdf; the secondary reference is .codex-src/systemc. Read the LRM first for the rule, then read the source to understand why the rule produces the behavior you see in a debugger.

End-to-End Datatypes Example

This fully compliant sc_main demonstrates the usage of 4-state logic (sc_logic), arbitrary width bit vectors (sc_bv), signed integer vectors (sc_int), and fixed-point math (sc_fixed).

#define SC_INCLUDE_FX // Required to enable fixed-point datatypes
#include <systemc>
 
SC_MODULE(DatatypesDemo) {
    SC_CTOR(DatatypesDemo) {
        SC_METHOD(demo_logic_and_vectors);
        SC_METHOD(demo_fixed_point);
    }
 
    void demo_logic_and_vectors() {
        // 1. 4-State Logic (0, 1, Z, X)
        sc_dt::sc_logic signal_state = sc_dt::Log_Z; // High-impedance
        
        // 2. Bit Vectors (2-state, arbitrary width)
        sc_dt::sc_bv<12> control_bus = "101011001111";
        
        // 3. Logic Vectors (4-state, arbitrary width)
        sc_dt::sc_lv<8> data_bus = "10ZX0011";
 
        // 4. Fixed-width signed integers
        sc_dt::sc_int<9> signed_val = -25;
        
        // Bit-slicing proxy demonstration:
        // Extract the upper 4 bits of control_bus and assign to a new 4-bit vector
        sc_dt::sc_bv<4> upper_nibble = control_bus.range(11, 8);
        
        std::cout << "--- Logic & Vectors ---" << std::endl;
        std::cout << "Signal: " << signal_state << std::endl;
        std::cout << "Control Bus: " << control_bus << std::endl;
        std::cout << "Upper Nibble: " << upper_nibble << std::endl;
        std::cout << "Signed Val (9-bit): " << signed_val << std::endl;
    }
 
    void demo_fixed_point() {
        std::cout << "--- Fixed Point Math ---" << std::endl;
        
        // 16 total bits, 4 bits for the integer part (12 bits fractional)
        sc_dt::sc_fixed<16, 4> a = 3.14159;
        sc_dt::sc_fixed<16, 4> b = -1.5;
        
        // The result of the multiplication is truncated/rounded automatically
        // according to the sc_fixed quantization modes defined in the LRM.
        sc_dt::sc_fixed<16, 4> result = a * b;
        
        std::cout << "3.14159 * -1.5 in Q4.12 fixed-point = " << result.to_double() << std::endl;
    }
};
 
int sc_main(int argc, char* argv[]) {
    DatatypesDemo demo("demo");
    sc_core::sc_start();
    return 0;
}

Type Breakdown & Kernel Implementations

Logic and Bit Vectors

• sc_logic: Represents four-state logic. Under the hood, it is an enum (Log_0, Log_1, Log_Z, Log_X) managed within a highly optimized class that provides truth tables for AND, OR, XOR logic gates using array lookups.
• sc_bv<W>: A two-state bit vector. Under the hood, it allocates an array of sc_dt::sc_digit (which maps to a 32-bit unsigned int in most architectures). sc_bv<64> allocates two integers. Bitwise operations are translated into standard CPU integer mask operations.
• sc_lv<W>: A four-state logic vector. Under the hood, it allocates two parallel data arrays: one for the base data value, and one for the control mask (to represent Z and X states mathematically).

Proxy Classes (range and bit)

When you call control_bus.range(11, 8), it does not allocate a new vector or a string. Under the hood, it returns an sc_subref (or sc_subref_r for read-only). This is a Proxy Object that holds a pointer to the original sc_bv array and the bit boundaries. It heavily overloads operator= to execute bit-masking directly into the memory of the original array, enabling syntax like bus.range(3,0) = 0xF; without memory leaks.

Fixed Width Integers

• sc_int<W> and sc_uint<W> (1 to 64 bits): Fast signed/unsigned fixed-width arithmetic. Under the hood, an sc_int<12> is stored as a full native 64-bit int64_t. The class overloads arithmetic operators and automatically applies bit-masks and sign-extensions to ensure the result exactly matches the behavior of a physical 12-bit ALU.
• sc_bigint<W> and sc_biguint<W>: Arbitrary precision arithmetic. Stored as an array of sc_digits. Multiplication involves software O(N^2) long-multiplication algorithms.

Fixed-Point (sc_fixed)

To use fixed-point types, you must define #define SC_INCLUDE_FX before including <systemc>. sc_fixed<WL, IWL> models word length (WL) and integer word length (IWL). The LRM provides exhaustive quantization and overflow modes (e.g., SC_RND, SC_TRN, SC_SAT) for DSP and AMS modeling, implemented using complex macro expansions and bit-shifts in sc_fxnum.

Practical Modeling Discipline

While bit selection proxies are syntactically convenient, dense bit-slicing equations are notoriously difficult to debug and slow down simulation due to proxy object construction. For Virtual Platforms and TLM, prefer standard C++ types (uint32_t, uint64_t) for data payloads and registers to maximize simulation speed, resorting to sc_bv only when bit-accurate pin modeling is explicitly required.