LRM Roadmap: How the Standards Fit Together

How to Read This Lesson

This lesson is an LRM bridge. We translate standard language into the questions you actually ask while debugging and reviewing models.

This site uses the LRMs in Docs/LRMs as reference sources, but the public lessons are written as explanations. The goal is to help you read the standards without feeling like you were dropped into an index. Furthermore, we dive into the Accellera C++ source code implementations to show you exactly how these standards are built under the hood.

The repository includes these reference manuals:

IEEE 1666-2023 SystemC Language Reference Manual: The core simulation kernel, events, and TLM standard.
SystemC AMS 2.0 Language Reference Manual: Analog and Mixed-Signal extensions.
SystemC CCI 1.0 Language Reference Manual: Configuration, Control, and Inspection API.
UVM-SystemC Language Reference Manual: Universal Verification Methodology for SystemC.

Source and LRM Trail

This chapter is the LRM bridge. The primary reference is Docs/LRMs/SystemC_LRM_1666-2023.pdf; the secondary reference is .codex-src/systemc. Read the LRM first for the rule, then read the source to understand why the rule produces the behavior you see in a debugger.

How to Think About the Stack

SystemC 1666 is the base language and simulation kernel. It defines modules, processes, events, time, ports, exports, channels, datatypes, reports, tracing, and the Transaction Level Modeling (TLM) 2.0 standard. All other LRMs build on this discrete-event foundation.

Under the Hood: Everything in SystemC derives from sc_core::sc_object. This creates a hierarchical object tree managed by sc_simcontext. The discrete-event scheduler (sc_simcontext::crunch()) is the heartbeat of all other standards.

SystemC AMS adds analog/mixed-signal modeling styles on top of SystemC. Its central ideas are timed data flow (TDF), conservative electrical networks, and linear signal flow (LSF), solving analog equations in conjunction with the discrete-event solver.

Under the Hood: AMS introduces a synchronization layer (sca_core::sca_implementation::sca_sync_obj). The TDF solver registers itself as an sc_module and schedules equation evaluations using sc_core::next_trigger(sc_time) or delta delays, effectively bridging continuous time matrices to the discrete-event m_timed_events queue.

SystemC CCI adds configuration, control, and inspection. It provides standard APIs to expose parameters (cci_param), broker access, and track where configuration values originated, heavily utilized in Virtual Platforms.

Under the Hood: CCI relies heavily on the underlying sc_object hierarchy string names (name()). The cci_broker_if interacts with a global map of parameters. When a parameter is accessed or mutated, CCI utilizes cci_value (which is effectively a JSON-like AST implemented using C++ union and std::string mappings) to serialize/deserialize typed data across IPs.

UVM-SystemC adds verification methodology: components, factory, phases, sequences, sequencers, configuration, reporting, TLM ports, and register abstractions, porting SystemVerilog UVM to C++.

Under the Hood: uvm_component inherits from sc_module. The UVM phasing mechanism leverages SystemC's sc_spawn to create dynamic threads that wait on phase barriers (sc_event). The factory pattern uses static initialization and C++ RTTI (typeid or macro-based registration) to instantiate objects by string names at runtime.

What "Between Learning Site and LRM" Means

An LRM strictly dictates legal syntax, elaboration phases, memory management, and standard compliance. It tells you what is defined. A learning site tells you how to think. These lessons aim to do both:

Name the LRM area explicitly.
Explain why it exists in the hardware modeling ecosystem.
Expose the exact Accellera GitHub repository C++ implementations (systemc, cci, uvm-systemc, systemc-ams).
Provide exhaustive, 100% compilable, end-to-end sc_main modeling patterns.
Warn about common C++ and SystemC mistakes.

If a lesson references standard definitions, treat it as exhaustive technical guidance compliant with the IEEE specs. Every code snippet provided in these LRM chapters is a fully independent model you can compile and run directly to observe the LRM's behavior firsthand.

Reading Order

If you are new, start with chapters 1 through 6. Then read the LRM bridge chapters:

SystemC 1666 Semantics and Core Classes: Elaboration, execution phases, and process macros.
Ports, Exports, Channels, Datatypes, and TLM: The structural and transaction-level backbone.
AMS Models of Computation: Timed Data Flow and solver synchronization.
CCI Parameters and Brokers: Tool-independent IP configuration.
UVM-SystemC Verification Architecture: Testbenches and constrained randomization.

That order ensures the LRMs become a structured technical guide rather than an overwhelming reference index.