For SystemC learners

Understand SystemC.
From model to kernel.

Build the mental model first. Then follow it through the LRM, the Accellera C++ source, and the virtual platforms engineers review in real architecture work.

Start as a beginner Explore the source

IEEE 1666 core | TLM-2.0 | AMS | CCI | UVM-SystemC | HLS | virtual platforms

137Carefully sequenced lessons
16Learning chapters
5Official LRM families
C++Source-first explanations

Beginner route

New to SystemC? Start here and take it one lesson at a time.

You do not need to understand the whole curriculum today. Finish these three steps first, then use the Next lesson button at the bottom of each page. The advanced chapters can wait.

Begin with step 1
Step 1

Check your C++ foundation

Review the small set of C++ ideas SystemC uses constantly. Skip ahead when these already feel familiar.

Review prerequisites
Step 2

Install and build once

Set up the library, CMake, and linking before you meet modules, processes, or simulation time.

Open setup guide
Step 3

Run your first model

Build a tiny working program, then continue lesson by lesson into the foundations chapter.

Build first model

New to SystemC?

Get the toolchain working before the abstractions pile up.

Start with the step-by-step setup lesson for Linux, Windows, CMake, library linking, and your first build. Then keep the examples open as copy-paste starting points while you learn.

Open the setup guide Browse runnable examples

Why this is not just another syntax list

Every serious topic is taught as contract, code, and engineering consequence.

Search visitors usually arrive with a narrow question: why did a process wake up, how should a TLM target respond, what belongs in a virtual platform, or which SystemC subset can HLS understand. The lessons answer those questions with the LRM rule, a runnable shape, and the implementation trail where that behavior becomes visible.

LRM-grounded explanations

SystemC, TLM-2.0, AMS, CCI, UVM-SystemC, and synthesis topics are explained from the standard outward.

Source-aware deep dives

Kernel behavior is connected to Accellera implementation paths without confusing implementation with portability.

Architecture-facing topics

Virtual platforms, microarchitecture modeling, SoC performance, DMI, routing, interrupts, and firmware traffic get their own path.

Search-guided learning routes

Start from the question you searched, then keep going.

Search Console shows readers arriving through SystemC tutorial, TLM, UVM-SystemC, synthesis, and example queries. These paths collect the right lessons so a quick answer can turn into a complete learning session.

learn systemc / systemc tutorial

SystemC tutorial

Beginner-safe path through modules, processes, events, ports, channels, and the scheduler.

Open route systemc tlm / generic payload / sockets

TLM-2.0 mastery

Payloads, blocking and non-blocking transport, DMI, debug transport, and temporal decoupling.

Open route run_test / uvm_component_utils / phases

UVM-SystemC

Components, factory, config database, phases, objections, sequences, reports, and TLM.

Open route systemc examples / systemc example

Runnable examples

Start from code, then follow the lesson that explains the rule behind the snippet.

Open route virtual prototype / SoC performance modeling

Virtual platforms

TLM routers, memory maps, peripherals, interrupts, DMI, CCI, and firmware traffic.

Open route systemc synthesis / synthesizable SystemC

SystemC HLS

Process styles, resets, datatypes, loop scheduling, and the synthesis subset.

Open route

Learn in layers

Do not stop at the macro. Follow the behavior.

A useful SystemC lesson should connect the model you write to the scheduler behavior you observe. That is why each deep dive keeps the public API, the portable LRM rule, and the source path in view.

01Write the model

Start from a compact example you can run.

02Read the contract

Separate portable behavior from implementation detail.

03Trace the kernel

Inspect the C++ path that makes the behavior visible.

Counter modelSC_METHOD
SC_MODULE(Counter) {
  sc_in<bool> clk;
  sc_out<unsigned> count;

  void tick() {
    count.write(count.read() + 1);
  }

  SC_CTOR(Counter) {
    SC_METHOD(tick);
    sensitive << clk.pos();
  }
};

Experienced reader shortcuts

Already modeling? Jump to the work on your desk.

These shortcuts are useful when you already know the basics. New learners should follow the beginner route above in order.

01Model the kernelModules, processes, events, delta cycles, ports, channels, and reports.02Build virtual platformsTLM sockets, payloads, routers, DMI, peripherals, ISS wrappers, and firmware traffic.03Read the sourceFollow public API calls into Accellera C++ implementation paths without confusing implementation with contract.04Use the wider ecosystemSystemC AMS, CCI, UVM-SystemC, and synthesis-oriented modeling practices.

Curriculum navigator

A deliberate route from first model to architecture review.

Lessons combine explanation, runnable examples, LRM context, and source trails.
Chapter 003 lessons

Start Here

C++ Prerequisites

Chapter 012 lessons

Foundations

Introduction to SystemC

Chapter 024 lessons

Core Modeling

Modules, Hierarchy, and Elaboration

Chapter 034 lessons

Communication

Ports, Interfaces, Exports, and Channels

Chapter 048 lessons

TLM and Platforms

TLM-2.0, Generic Payloads, and Sockets

Chapter 058 lessons

Source Internals

SystemC Source Map & LRM Alignment

Chapter 063 lessons

Practice

Virtual Platform Patterns

Chapter 0711 lessons

SystemC 1666-2023 LRM

LRM Roadmap: How the Standards Fit Together

Chapter 0813 lessons

SystemC AMS

SystemC AMS (Analog/Mixed-Signal)

Chapter 0914 lessons

SystemC CCI

Configuration, Control & Inspection (CCI)

Chapter 1017 lessons

UVM-SystemC

System Verification, SCV & UVM-SystemC

Chapter 1119 lessons

Advanced Core Semantics

The Execution Phases

Chapter 1213 lessons

Virtual Platform Construction

VP Architecture & Design

Chapter 139 lessons

Modeling Best Practices

Modeling Best Practices: Abstraction

Chapter 148 lessons

Synthesis Subset

Introduction to High-Level Synthesis (HLS)

Chapter 151 lessons

Appendices & FAQ

Beginner Pitfalls & FAQ

LRM contract + C++ implementation

Read SystemC like an engineer, not like a list of macros.

Each deep-dive keeps two views in frame. The LRM tells you which behavior is portable. The source trail shows one implementation path through the kernel so debugging and code review become less mysterious.

Open the source-reading workflow
sc_simcontext scheduling and delta-cycle progression
sc_module hierarchy, naming, and elaboration callbacks
sc_signal deferred updates and writer policies
sc_port, sc_export, interfaces, and binding resolution
TLM sockets, generic payloads, DMI, and memory managers
SC_THREAD coroutine switching around wait() and events
AMS solver boundaries, CCI brokers, and UVM phasing

Optional visual navigation

Take the curriculum into Orbit.

Switch views from the top bar. The galaxy becomes your chapter map while every lesson keeps its technical depth.

Start with foundations

Guided video courses

Go deeper when you want a structured, end-to-end route.

The written curriculum stays free. Premium video courses are being planned for readers who want guided builds, walkthroughs, and a focused learning sequence.

Planned course

SystemC from Scratch

A guided video path from setup and first modules to confident kernel-level debugging.

Request early access
Planned course

TLM-2.0 Mastery

Sockets, payloads, timing styles, DMI, memory management, protocol phases, and VP performance.

Request early access
Planned course

Integrating SystemC with UVM

Build verification environments with UVM-SystemC components, phases, sequences, reporting, and TLM.

Request early access